At the Open Innovation Platform Ecosystem Forum in Santa Clara on Wednesday, chip foundry TSMC provided an update (via EE Times) on the progress of its forthcoming technology nodes, several of which would be candidates for upcoming Apple chips. Most notably, the company’s first 7-nanometer process node has already had several tape-outs (finalized designs) and expects to reach volume capacity in 2018.
TSMC’s 10 nm node, which first showed up in Apple’s A10X chip in the iPad Pro, followed by the A11, has been fraught with issues (paid link) such as low chip yield and performance short of initial expectations. TSMC looks to change its fortune with the new 7 nm node, which would be suitable for the successor to the A11 chip given current timelines.
In addition to the 7 nm node, TSMC also shared information on the follow-up revision to this node, dubbed, N7+. Featuring the long-beleaguered Extreme Ultraviolet Lithography (EUV), the revision would promise 20 percent better density, around 10 percent higher speeds, or 15 percent lower power with other factors held constant.
While EUV has faced delays for over a decade at this point, it seems to finally be coming to fruition, and a 2019 volume availability update would allow Apple to update its chip process in subsequent years yet again. Apple had previously updated process nodes with every iPhone since the transition to 3GS before being forced to use TSMC’s 16 nm node in consecutive years with the A9 and A10. Moving forward, that annual cadence is again in jeopardy as chip foundries deal with the realities of physics and minimum transistor geometry sizes.
TSMC also unveiled some low power and low leakage processes that are suitable for Apple’s other custom designs, such as its line of wireless chips like the W1 and successor W2. TSMC is targeting availability next year of a 22 nm ultra low leakage node, which is suitable for analog and RF designs such as cellular basebands or Wi-Fi chips.
This will ultimately help Apple further lower power consumption on the Apple Watch and headphones featuring the W line of wireless chips. It is also likely to be adopted by Qualcomm for its line of modem products. The W1 and W2 manufacturing processes are not currently publicly known, but it is likely that one of TSMC’s RF-focused processes powers the Apple chips.
Finally, TSMC announced a revision of its integrated fan-out packaging process (InFO) that is targeted at integrating high bandwidth memory (HBM) into the assembly, dubbed InFO-MS. HBM has generated a lot of interest from applications where very high sustained memory bandwidths are desired, such as consumer graphics cards.
HBM and similar standards such as Wide I/O promise not only to improve memory bandwidth, but also improve power consumption for a given bandwidth, making it a suitable evolution for mobile SoC designs. This type of memory interface has yet to appear in a mobile design, though it should be considered a near-term eventuality. Despite advances in mobile memory, it still lags behind desktop and laptop systems in total bandwidth, which can be important in some tasks such as graphics rendering.
Tags: TSMC, W1, A12, W2
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